1. Field of the Invention
The present invention relates to a bus system and a master device used in the bus system.
2. Description of the Background Art
A microcomputer built into an electronic data appliance or a household electrical appliance has a bus system. Such a bus system includes a uni-directional bus and/or a bidirectional bus that is connected to a master device and slave devices. Here, a master device refers to a device, such as a CPU or a Direct Memory Access Controller (DMAC), that determines whether to permit other devices to access a slave device via a bus, and a slave device refers to a device, such as a memory or an input/output (I/O) controller, which is accessed according to an access permission signal from the master device.
In such a system, the wiring that forms the buses takes up a large proportion of the area of a printed circuit board (PCB). As these conductors are subject to noise from both inside and outside of the appliance, a master device and slave devices connected to the buses drive the buses by providing relatively large currents.
Driving of a bus with a large current stabilizes the electric potential of the bus during an access period, but at the same time destabilizes the bus potential during a non-access period where master devices and slave devices are not permitted to perform accesses via the bus. This may cause a processor or a slave device connected to the bus to malfunction, or even lead to a breakdown of the processor or the slave device. FIG. 1A is a timing chart showing states where the bus potential is undefined during non-access periods.
The timing chart shows an access permission signal outputted by a master device and the bus potential during periods 131-135. A period in which the access permission is signal is high indicates an access period. As is clear from the chart, the bus potential is low in access period 132 and high in access period 134, while it is undefined without reaching to either a high or low level in non-access periods 131, 133, and 135.
The following explains a method conventionally used in a bus system to stabilize the bus potential during a non-access period.
In the conventional method, pull-up resistors are connected to a bidirectional bus to stabilize a bus potential as shown in FIG. 1B. This figure shows the construction of a bus system in which a CPU (a master device) and three devices (slave devices) are connected to a uni-directional bus and the bidirectional bus that is connected to pull-up resistors RI. The uni-directional bus carries addresses, and the bidirectional bus carries data. FIG. 1C is a timing chart showing an access permission signal and a bus potential in the bus system shown in FIG. 1B. The access permission signal is similar to that shown in FIG. 1A, while the bus potential is different, which is to say, the bus potential is high and stabilized due to the pull-up resistors R1 during non-access periods 131, 133, and 135, during which the bus potential is undefined in FIG. 1A.
This conventional method, however, has a problem during an access period where the bus potential is low. This is to say, when the potential of the bidirectional bus is low, currents flow away from the power-supply line to ground through the pull-up resistors RI. As a result, power consumption increases during access periods. As another method to stabilize a bus potential during a non-access period, pull-down resistors can be connected between the bidirectional bus and ground to fix a bus potential at 0v. In this case, however, currents flows away through the pull-down resistors to ground during an access period where the bus potential is high, and therefore power consumption increases as in the conventional method that uses pull-up resistors.
An object of the present invention is to provide a master device and a bus system that can stabilize the bus potential during non-access periods without increasing power consumption during access periods.
The above object can be achieved by a master device that includes a bus and at least one device, wherein the bus connects the master device with the device, the master device including: a first storing unit for storing data to be written into a device; a second storing unit for storing dummy data that stabilizes an electrical potential of the bus; a first management unit for managing whether the system is in an access state in which the master device permits an access to or from one device or a non-access state in which the master device permits an access to or from none of devices; an output selecting unit for outputting, if the system is in the access state and data is to be written into a device, the data in the first storing unit, and for outputting the dummy data in the second storing unit it the system is in the non-access state; and a driving unit for driving, if the output selecting unit outputs one of the data and the dummy data, the bus with a predetermined current to have the bus transfer the one of the data and the dummy data.
With the stated construction, the output selecting unit of the master device selectively outputs dummy data stored in the second storing unit during a non-access period so that the bus potential during this period can be stabilized. As a result, the system of the present invention does not require the pull-resistors that have been used in a conventional bus system. With this conventional bus system, which raises the bus potential during both an access period and a non-access period using the pull-up resistors, currents flow away through the pull-up resistors during an access period where the bus potential is low, while with the present system, there is no possibility of losing currents during this period, and therefore less electricity is used.
Here, the second storing unit may include a latch unit for latching data as the dummy data, the data having been outputted most recently by the first storing unit via the output selecting unit to the input terminal.
For the stated construction, the master device outputs data that the access data storing unit outputted during the latest write enable period as dummy data during a non-access period that immediately follows the write enable period. As a result, the bus potential will not change at a transition from this write enable period to the following non-access period, and therefore the master device uses even less electricity.
Here, the master device may include a separating unit for separating, from data on the bus, data read from a device most recently when the system is in the read enable state, wherein the second storing unit may include a latch unit for latching the separated read data as the dummy data
For the stated construction, the master device outputs data that the latch unit latched during the latest read enable period as dummy data during a non-access period that immediately follows the read enable period. As a result, the bus potential will not change at a transition from this read enable period to the following non-access period, and therefore the master device uses less electricity.